Documentation

Return if the Identifier is in a '(ModDecl ann)'.

Find the last assignment of a specific wire/reg to an expression, and returns that expression.

Transforms an expression by replacing an Identifier with an expression. This is used inside transformOf and traverseExpr to replace the Identifier recursively.

Replaces the identifier recursively in an expression.

Nest expressions for a specific Identifier. If the Identifier is not found, the AST is not changed.

This could be improved by instead of only using the last assignment to the wire that one finds, to use the assignment to the wire before the current expression. This would require a different approach though.

Replaces an identifier by a expression in all the module declaration.

Nest variables in the format w[0-9]* up to a certain number.

Add a Module Instantiation using ModInst from the first module passed to it to the body of the second module. It first has to make all the inputs into reg.

>>> render $ instantiateMod m main
module main;
  wire [(3'h4):(1'h0)] y;
  reg [(3'h4):(1'h0)] x;
  m m1(y, x);
endmodule

Instantiate without adding wire declarations. It also does not count the current instantiations of the same module.

>>> GenVerilog $ instantiateMod_ m
m m(y, x);

Instantiate without adding wire declarations. It also does not count the current instantiations of the same module.

>>> GenVerilog $ instantiateModSpec_ "_" m
m m(.y(y), .x(x));

Initialise all the inputs and outputs to a module.

>>> GenVerilog $ initMod m
module m(y, x);
  output wire [(3'h4):(1'h0)] y;
  input wire [(3'h4):(1'h0)] x;
endmodule

Make an Identifier from and existing Identifier and an object with a Show instance to make it unique.

Make top level module for equivalence verification. Also takes in how many modules to instantiate.

Make a top module with an assert that requires y_1 to always be equal to y_2, which can then be proven using a formal verification tool.

Simplify an Expr by using constants to remove BinaryOperator and simplify expressions. To make this work effectively, it should be run until no more changes were made to the expression.

>>> GenVerilog . simplify $ (Id "x") + 0
x

>>> GenVerilog . simplify $ (Id "y") + (Id "x")
(y + x)

Remove all Identifier that do not appeare in the input list from an Expr. The identifier will be replaced by 1'b0, which can then later be simplified further.

>>> GenVerilog . removeId ["x"] $ Id "x" + Id "y"
(x + (1'h0))

Provide declarations for all the ports that are passed to it. If they are registers, it should assign them to 0.