| Copyright | (c) 2018-2019 Yann Herklotz |
|---|---|
| License | GPL-3 |
| Maintainer | yann [at] yannherklotz [dot] com |
| Stability | experimental |
| Portability | POSIX |
| Safe Haskell | None |
| Language | Haskell2010 |
Verismith.Verilog.CodeGen
Contents
Description
This module generates the code from the Verilog AST defined in Verismith.Verilog.AST.
Synopsis
- newtype GenVerilog a = GenVerilog {
- unGenVerilog :: a
- class Source a where
- render :: Source a => a -> IO ()
Code Generation
newtype GenVerilog a Source #
Constructors
| GenVerilog | |
Fields
| |
Instances
| Data a => Data (GenVerilog a) Source # | |
Defined in Verismith.Verilog.CodeGen Methods gfoldl :: (forall d b. Data d => c (d -> b) -> d -> c b) -> (forall g. g -> c g) -> GenVerilog a -> c (GenVerilog a) # gunfold :: (forall b r. Data b => c (b -> r) -> c r) -> (forall r. r -> c r) -> Constr -> c (GenVerilog a) # toConstr :: GenVerilog a -> Constr # dataTypeOf :: GenVerilog a -> DataType # dataCast1 :: Typeable t => (forall d. Data d => c (t d)) -> Maybe (c (GenVerilog a)) # dataCast2 :: Typeable t => (forall d e. (Data d, Data e) => c (t d e)) -> Maybe (c (GenVerilog a)) # gmapT :: (forall b. Data b => b -> b) -> GenVerilog a -> GenVerilog a # gmapQl :: (r -> r' -> r) -> r -> (forall d. Data d => d -> r') -> GenVerilog a -> r # gmapQr :: forall r r'. (r' -> r -> r) -> r -> (forall d. Data d => d -> r') -> GenVerilog a -> r # gmapQ :: (forall d. Data d => d -> u) -> GenVerilog a -> [u] # gmapQi :: Int -> (forall d. Data d => d -> u) -> GenVerilog a -> u # gmapM :: Monad m => (forall d. Data d => d -> m d) -> GenVerilog a -> m (GenVerilog a) # gmapMp :: MonadPlus m => (forall d. Data d => d -> m d) -> GenVerilog a -> m (GenVerilog a) # gmapMo :: MonadPlus m => (forall d. Data d => d -> m d) -> GenVerilog a -> m (GenVerilog a) # | |
| Source a => Show (GenVerilog a) Source # | |
Defined in Verismith.Verilog.CodeGen Methods showsPrec :: Int -> GenVerilog a -> ShowS # show :: GenVerilog a -> String # showList :: [GenVerilog a] -> ShowS # | |
| Eq a => Eq (GenVerilog a) Source # | |
Defined in Verismith.Verilog.CodeGen | |
| Ord a => Ord (GenVerilog a) Source # | |
Defined in Verismith.Verilog.CodeGen Methods compare :: GenVerilog a -> GenVerilog a -> Ordering # (<) :: GenVerilog a -> GenVerilog a -> Bool # (<=) :: GenVerilog a -> GenVerilog a -> Bool # (>) :: GenVerilog a -> GenVerilog a -> Bool # (>=) :: GenVerilog a -> GenVerilog a -> Bool # max :: GenVerilog a -> GenVerilog a -> GenVerilog a # min :: GenVerilog a -> GenVerilog a -> GenVerilog a # | |
| Mutate a => Mutate (GenVerilog a) Source # | |
Defined in Verismith.Verilog.Mutate Methods mutExpr :: (Expr -> Expr) -> GenVerilog a -> GenVerilog a Source # | |
Source class which determines that source code is able to be generated
from the data structure using genSource. This will be stored in Text and
can then be processed further.
Instances
| Source ConstExpr Source # | |
| Source ContAssign Source # | |
Defined in Verismith.Verilog.CodeGen Methods genSource :: ContAssign -> Text Source # | |
| Source Delay Source # | |
| Source Event Source # | |
| Source Expr Source # | |
| Source Identifier Source # | |
Defined in Verismith.Verilog.CodeGen Methods genSource :: Identifier -> Text Source # | |
| Source LVal Source # | |
| Source Port Source # | |
| Source PortDir Source # | |
| Source PortType Source # | |
| Source Task Source # | |
| Source UnaryOperator Source # | |
Defined in Verismith.Verilog.CodeGen Methods genSource :: UnaryOperator -> Text Source # | |
| Show ann => Source (ModDecl ann) Source # | |
| Show ann => Source (ModItem ann) Source # | |
| Show ann => Source (SourceInfo ann) Source # | |
Defined in Verismith.Verilog.CodeGen Methods genSource :: SourceInfo ann -> Text Source # | |
| Show ann => Source (Statement ann) Source # | |
| Show ann => Source (Verilog ann) Source # | |