verismith-1.1.0: Random verilog generation and simulator testing.
Copyright(c) 2021 Yann Herklotz
LicenseGPL-3
Maintaineryann [at] yannherklotz [dot] com
Stabilityexperimental
PortabilityPOSIX
Safe HaskellNone
LanguageHaskell2010

Verismith.EMI

Description

Equivalence modulo inputs (EMI) testing. This file should get an existing design, and spit out a modified design that is equivalent under some specific values of the extra inputs.

Synopsis

Documentation

data EMIInputs a Source #

Constructors

EMIInputs [Identifier] 
EMIOrig a 

Instances

Instances details
Show a => Show (EMIInputs a) Source # 
Instance details

Defined in Verismith.EMI

Eq a => Eq (EMIInputs a) Source # 
Instance details

Defined in Verismith.EMI

Methods

(==) :: EMIInputs a -> EMIInputs a -> Bool #

(/=) :: EMIInputs a -> EMIInputs a -> Bool #

Ord a => Ord (EMIInputs a) Source # 
Instance details

Defined in Verismith.EMI

proceduralEMI :: SourceInfo a -> Config -> Gen (SourceInfo (EMIInputs a)) Source #

Procedural generation method for random Verilog. Uses internal Reader and State to keep track of the current Verilog code structure.

makeTopEMI :: Int -> ModDecl (EMIInputs ann) -> (ModDecl (EMIInputs ann), [Identifier]) Source #

Make top level module for equivalence verification. Also takes in how many modules to instantiate.

makeTopAssertEMI :: Bool -> ModDecl (EMIInputs ann) -> (ModDecl (EMIInputs ann), [Identifier]) Source #

Make a top module with an assert that requires y_1 to always be equal to y_2, which can then be proven using a formal verification tool.

p :: Show a => ModDecl a -> IO () Source #

p2 :: Show a => SourceInfo a -> IO () Source #

top :: IO () Source #

top2 :: IO () Source #