Generation methods

Procedural generation method for random Verilog. Uses internal Reader and State to keep track of the current Verilog code structure.

Samples the Gen directly to generate random Verilog using the Text as the name of the main module and the configuration Config to influence the generation.

Given a Text and a Config will generate a '(SourceInfo ann)' which has the top module set to the right name.

Sampled and wrapped into a '(SourceInfo ann)' with the given top module name.

Generates a random large number, which can also be negative.

Generates a random size for a wire so that it is not too small and not too large.

Generates a random range by using the wireSize and 0 as the lower bound.

Generate a random bit vector using largeNum.

Return a random BinaryOperator. This currently excludes BinDiv, BinMod because they can take a long time to synthesis, and BinCEq, BinCNEq, because these are not synthesisable. BinPower is also excluded because it can only be used in conjunction with base powers of 2 which is currently not enforced.

Generate a random UnaryOperator.

Generate a random ConstExpr by using the current context of Parameter.

The list of safe Expr, meaning that these will not recurse and will end the Expr generation.

List of Expr that have the chance to recurse and will therefore not be used when the expression grows too large.

Generate a random expression from the Context with a guarantee that it will terminate using the list of safe Expr.

Make a new name with a prefix and the current nameCounter. The nameCounter is then increased so that the label is unique.

Makes a new Identifier and then checks if the Port already exists, if it does the existant Port is returned, otherwise a new port is created with newPort. This is used subsequently in all the functions to create a port, in case a port with the same name was already created. This could be because the generation is currently in the other branch of an if-statement.

Creates a new port based on the current name counter and adds it to the current context. It will be added to the _wires list.

Creates a new port based on the current name counter and adds it to the current context. It will be added to the _nonblocking list.

Creates a new port based on the current name counter and adds it to the current context. It will be added to the _blocking list.

Generates a random continuous assignment and assigns it to a random wire that is created.

Converts a Port to an LVal by only keeping the Identifier of the Port.

Generate a random assignment and assign it to a random Reg.

Generate a random Statement safely, by also increasing the depth counter.

Generate a random conditional Statement. The nameCounter is reset between branches so that port names can be reused. This is safe because if a Port is not reused, it is left at 0, as all the Reg are initialised to 0 at the start.

Generate a random for loop by creating a new variable name for the counter and then generating random statements in the body.

Choose a Statement to generate.

Generate a sequential always block which is dependent on the clock.

Instantiate a module, where the outputs are new nets that are created, and the inputs are taken from existing ports in the context.

1 is subtracted from the inputs for the length because the clock is not counted and is assumed to be there, this should be made nicer by filtering out the clock instead. I think that in general there should be a special representation for the clock.

Generates a module instance by also generating a new module if there are not enough modules currently in the context. It keeps generating new modules for every instance and for every level until either the deepest level is achieved, or the maximum number of modules are reached.

If the maximum number of levels are reached, it will always pick an instance from the current context. The problem with this approach is that at the end there may be many more than the max amount of modules, as the modules are always set to empty when entering a new level. This is to fix recursive definitions of modules, which are not defined.

One way to fix that is to also decrement the max modules for every level, depending on how many modules have already been generated. This would mean there would be moments when the module cannot generate a new instance but also not take a module from the current context. A fix for that may be to have a default definition of a simple module that is used instead.

Another different way to handle this would be to have a probability of taking a module from a context or generating a new one.

Generate a random module item.

Generate a random ConstExpr by using the current context of Parameters.

Generate a random Parameter and assign it to a constant expression which it will be initialised to. The assumption is that this constant expression should always be able to be evaluated with the current context of parameters.

Generates a module definition randomly. It always has one output port which is set to y. The size of y is the total combination of all the locally defined wires, so that it correctly reflects the internal state of the module.

Runs a StateGen for a random number of times, limited by an Int that is passed to it.

Returns the probability from the configuration.

Gets the current probabilities from the State.

Should resize a port that connects to a module port if the latter is larger. This should not cause any problems if the same net is used as input multiple times, and is resized multiple times, as it should only get larger.

Either return the Identifier that was passed to it, or generate a new Identifier based on the current nameCounter.

Evaluate a range to an integer, and cast it back to a range.

Calculate a range to an int by maybe resizing the ranges to a value.