Datatype representing a single transaction request sent from a Wishbone Master to a Wishbone Slave

Create a stalling wishbone Standard circuit.

Create a wishbone Standard circuit to drive other circuits.

Circuit which validates the wishbone communication signals between a master and a slave circuit.

Halts execution using error when a "common sense" spec validation occurs.

N.B. Not synthesisable.

Circuit which validates the wishbone communication signals between a master and a slave circuit.

Halts execution using error when a spec validation occurs.

N.B. Not synthesisable.

Given a wishbone manager and wishbone subordinate, connect them and sample their forward and backward channel lazily.

Test a wishbone Standard circuit against a pure model.

Generate a random Wishbone transfer based on an address range and a payload generator.

Simulates a wishbone manager and subordinate and returns their transactions. The results are filtered to only include transactions that have bus activity, for a version that includes all cycles, see sampleUnfiltered.

Simulates a wishbone manager and subordinate and the state of the bus for every cycle. For a time independent version that only includes transactions, see sample.

Interpret a WishboneM2S as a WishboneMasterRequest. Only works for valid requests and performs no checks.

Checks equality for relevant parts of a WishboneS2M response based on the corresponding WishboneMasterRequest. For a Write request, the readData field is ignored, for a Read request only the selected bytes are checked.

>>> 
:{
let
  readReqA = Read (0 :: BitVector 32) (0b1111 :: BitVector 4)
  readReqB = Read (0 :: BitVector 32) (0b0001 :: BitVector 4)
  writeReq = Write (0 :: BitVector 32) (0b1111 :: BitVector 4) (0x12345678 :: BitVector 32)
  s2mA = (emptyWishboneS2M @4)
    { readData = 0x00FF
    , acknowledge = True
    , err = False
    , retry = False
    }
  s2mB = (emptyWishboneS2M @4)
    { readData = 0xFFFF
    , acknowledge = True
    , err = False
    , retry = False
    }
  s2mC = (emptyWishboneS2M @4)
    { readData = deepErrorX ""
    , acknowledge = True
    , err = False
    , retry = False
    }
:}

>>> eqWishboneS2M readReqA s2mA s2mB
False
>>> eqWishboneS2M readReqB s2mA s2mB
True
>>> eqWishboneS2M writeReq s2mA s2mB
True
>>> eqWishboneS2M writeReq s2mA s2mC
True