-- |
-- Module      : Verismith.Circuit
-- Description : Definition of the circuit graph.
-- Copyright   : (c) 2018-2019, Yann Herklotz
-- License     : GPL-3
-- Maintainer  : yann [at] yannherklotz [dot] com
-- Stability   : experimental
-- Portability : POSIX
--
-- Definition of the circuit graph.
module Verismith.Circuit
  ( -- * Circuit
    Gate (..),
    Circuit (..),
    CNode (..),
    CEdge (..),
    fromGraph,
    generateAST,
    rDups,
    rDupsCirc,
    randomDAG,
    genRandomDAG,
  )
where

import Control.Lens
import Hedgehog (Gen)
import qualified Hedgehog.Gen as Hog
import Verismith.Circuit.Base
import Verismith.Circuit.Gen
import Verismith.Circuit.Random
import Verismith.Verilog.AST
import Verismith.Verilog.Mutate

fromGraph :: Gen (ModDecl ann)
fromGraph :: forall ann. Gen (ModDecl ann)
fromGraph = do
  Circuit
gr <- Circuit -> Circuit
rDupsCirc (Circuit -> Circuit)
-> GenT Identity Circuit -> GenT Identity Circuit
forall (f :: * -> *) a b. Functor f => (a -> b) -> f a -> f b
<$> Size -> GenT Identity Circuit -> GenT Identity Circuit
forall (m :: * -> *) a. MonadGen m => Size -> m a -> m a
Hog.resize Size
100 GenT Identity Circuit
randomDAG
  ModDecl ann -> Gen (ModDecl ann)
forall a. a -> GenT Identity a
forall (m :: * -> *) a. Monad m => a -> m a
return (ModDecl ann -> Gen (ModDecl ann))
-> ModDecl ann -> Gen (ModDecl ann)
forall a b. (a -> b) -> a -> b
$
    ModDecl ann -> ModDecl ann
forall ann. ModDecl ann -> ModDecl ann
initMod
      (ModDecl ann -> ModDecl ann)
-> ([ModDecl ann] -> ModDecl ann) -> [ModDecl ann] -> ModDecl ann
forall b c a. (b -> c) -> (a -> b) -> a -> c
. [ModDecl ann] -> ModDecl ann
forall a. HasCallStack => [a] -> a
head
      ([ModDecl ann] -> ModDecl ann) -> [ModDecl ann] -> ModDecl ann
forall a b. (a -> b) -> a -> b
$ Int -> Verilog ann -> Verilog ann
forall ann. Int -> Verilog ann -> Verilog ann
nestUpTo Int
5 (Circuit -> Verilog ann
forall ann. Circuit -> Verilog ann
generateAST Circuit
gr)
        Verilog ann
-> Getting (Endo [ModDecl ann]) (Verilog ann) (ModDecl ann)
-> [ModDecl ann]
forall s a. s -> Getting (Endo [a]) s a -> [a]
^.. ([ModDecl ann] -> Const (Endo [ModDecl ann]) [ModDecl ann])
-> Verilog ann -> Const (Endo [ModDecl ann]) (Verilog ann)
(Unwrapped (Verilog ann)
 -> Const (Endo [ModDecl ann]) (Unwrapped (Verilog ann)))
-> Verilog ann -> Const (Endo [ModDecl ann]) (Verilog ann)
forall s t. Rewrapping s t => Iso s t (Unwrapped s) (Unwrapped t)
Iso
  (Verilog ann)
  (Verilog ann)
  (Unwrapped (Verilog ann))
  (Unwrapped (Verilog ann))
_Wrapped
          (([ModDecl ann] -> Const (Endo [ModDecl ann]) [ModDecl ann])
 -> Verilog ann -> Const (Endo [ModDecl ann]) (Verilog ann))
-> ((ModDecl ann -> Const (Endo [ModDecl ann]) (ModDecl ann))
    -> [ModDecl ann] -> Const (Endo [ModDecl ann]) [ModDecl ann])
-> Getting (Endo [ModDecl ann]) (Verilog ann) (ModDecl ann)
forall b c a. (b -> c) -> (a -> b) -> a -> c
. (ModDecl ann -> Const (Endo [ModDecl ann]) (ModDecl ann))
-> [ModDecl ann] -> Const (Endo [ModDecl ann]) [ModDecl ann]
forall (t :: * -> *) (f :: * -> *) a b.
(Traversable t, Applicative f) =>
(a -> f b) -> t a -> f (t b)
forall (f :: * -> *) a b.
Applicative f =>
(a -> f b) -> [a] -> f [b]
traverse