verismith-1.1.0: Random verilog generation and simulator testing.
Copyright(c) 2021 Yann Herklotz
LicenseGPL-3
Maintaineryann [at] yannherklotz [dot] com
Stabilityexperimental
PortabilityPOSIX
Safe HaskellNone
LanguageHaskell2010

Verismith.Shuffle

Description

Shuffles the Verilog file around a bit.

Synopsis

Documentation

shuffleLinesModule :: MonadGen m => ModDecl a -> m (ModDecl a) Source #

Shuffles assign statements and always blocks in a Verilog file.

applyModules :: MonadGen m => (ModDecl a -> m (ModDecl a)) -> SourceInfo a -> m (SourceInfo a) Source #