| Safe Haskell | None |
|---|---|
| Language | GHC2021 |
Protocols.Experimental.Wishbone.Standard
Description
Circuits and utilities for working with Standard-mode Wishbone circuits.
Synopsis
- roundrobin :: forall (n :: Nat) (dom :: Domain) (addressBits :: Nat) (dataBytes :: Nat). (KnownNat n, HiddenClockResetEnable dom, KnownNat addressBits, KnownNat dataBytes, 1 <= n) => Circuit (Wishbone dom 'Standard addressBits dataBytes) (Vec n (Wishbone dom 'Standard addressBits dataBytes))
- sharedBus :: forall (n :: Nat) (m :: Nat) (dom :: Domain) (addressBits :: Nat) (dataBytes :: Nat). (KnownNat n, KnownNat m, HiddenClockResetEnable dom, KnownNat addressBits, KnownNat dataBytes) => (Signal dom (Index n, Index m, Vec n (WishboneM2S addressBits dataBytes)) -> Signal dom (Index n, Index m)) -> Circuit (Vec n (Wishbone dom 'Standard addressBits dataBytes)) (Vec m (Wishbone dom 'Standard addressBits dataBytes))
- crossbarSwitch :: forall (n :: Nat) (m :: Nat) (dom :: Domain) (addressBits :: Nat) (dataBytes :: Nat). (KnownNat n, KnownNat m, KnownDomain dom, KnownNat addressBits, KnownNat dataBytes) => Circuit (CSignal dom (Vec n (Index m)), Vec n (Wishbone dom 'Standard addressBits dataBytes)) (Vec m (Wishbone dom 'Standard addressBits dataBytes))
- data MemoryDelayState
- memoryWb :: forall (dom :: Domain) (addressBits :: Nat) (dataBytes :: Nat). (KnownDomain dom, KnownNat addressBits, KnownNat dataBytes, HiddenClockResetEnable dom) => (Signal dom (BitVector addressBits) -> Signal dom (Maybe (BitVector addressBits, BitVector (dataBytes * 8))) -> Signal dom (BitVector (dataBytes * 8))) -> Circuit (Wishbone dom 'Standard addressBits dataBytes) ()
Documentation
roundrobin :: forall (n :: Nat) (dom :: Domain) (addressBits :: Nat) (dataBytes :: Nat). (KnownNat n, HiddenClockResetEnable dom, KnownNat addressBits, KnownNat dataBytes, 1 <= n) => Circuit (Wishbone dom 'Standard addressBits dataBytes) (Vec n (Wishbone dom 'Standard addressBits dataBytes)) Source #
Distribute requests amongst N slave circuits
Arguments
| :: forall (n :: Nat) (m :: Nat) (dom :: Domain) (addressBits :: Nat) (dataBytes :: Nat). (KnownNat n, KnownNat m, HiddenClockResetEnable dom, KnownNat addressBits, KnownNat dataBytes) | |
| => (Signal dom (Index n, Index m, Vec n (WishboneM2S addressBits dataBytes)) -> Signal dom (Index n, Index m)) | Function used to select which M-S pair should be connected next. |
| -> Circuit (Vec n (Wishbone dom 'Standard addressBits dataBytes)) (Vec m (Wishbone dom 'Standard addressBits dataBytes)) |
General-purpose shared-bus with N masters and M slaves.
A selector signal is used to compute the next M-S pair.
crossbarSwitch :: forall (n :: Nat) (m :: Nat) (dom :: Domain) (addressBits :: Nat) (dataBytes :: Nat). (KnownNat n, KnownNat m, KnownDomain dom, KnownNat addressBits, KnownNat dataBytes) => Circuit (CSignal dom (Vec n (Index m)), Vec n (Wishbone dom 'Standard addressBits dataBytes)) (Vec m (Wishbone dom 'Standard addressBits dataBytes)) Source #
Crossbar switch allowing N masters to be routed dynamically to M slaves.
data MemoryDelayState Source #
State used to guarantee correct response timing in memoryWb.
Instances
| NFDataX MemoryDelayState Source # | |||||
Defined in Protocols.Experimental.Wishbone.Standard Methods deepErrorX :: String -> MemoryDelayState # hasUndefined :: MemoryDelayState -> Bool # ensureSpine :: MemoryDelayState -> MemoryDelayState # rnfX :: MemoryDelayState -> () # | |||||
| Generic MemoryDelayState Source # | |||||
Defined in Protocols.Experimental.Wishbone.Standard Associated Types
Methods from :: MemoryDelayState -> Rep MemoryDelayState x # to :: Rep MemoryDelayState x -> MemoryDelayState # | |||||
| type Rep MemoryDelayState Source # | |||||
Defined in Protocols.Experimental.Wishbone.Standard | |||||
memoryWb :: forall (dom :: Domain) (addressBits :: Nat) (dataBytes :: Nat). (KnownDomain dom, KnownNat addressBits, KnownNat dataBytes, HiddenClockResetEnable dom) => (Signal dom (BitVector addressBits) -> Signal dom (Maybe (BitVector addressBits, BitVector (dataBytes * 8))) -> Signal dom (BitVector (dataBytes * 8))) -> Circuit (Wishbone dom 'Standard addressBits dataBytes) () Source #
Memory component circuit using a specific RAM function
This circuit uses Standard mode and only supports the classic cycle type.
Because of this, the data rate is limited by the one-cycle delay of the RAM
function when reading and the inserted stall-cycle.
The data rate could be increased by using registered feedback cycles or by using a pipelined circuit which would eliminate one wait cycle.
Since the underlying block RAM operates on the whole bitvector, the only
accepted bus selector value is maxBound. All other bus selector values
will cause an ERR response.
TODO create pipelined memory circuit