| Copyright | (C) 2017 Google Inc |
|---|---|
| License | BSD2 (see the file LICENSE) |
| Maintainer | Christiaan Baaij <christiaan.baaij@gmail.com> |
| Safe Haskell | None |
| Language | Haskell2010 |
Clash.Xilinx.DDR
Contents
Description
DDR primitives for Xilinx FPGAs
For general information about DDR primitives see Clash.Explicit.DDR.
For more information about the Xilinx DDR primitives see:
- Vivado Design Suite 7 Series FPGA and Zynq-7000 All Programmable SoC Libraries Guide, UG953 (v2022.2) October 19, 2022, p369-371, p477-479, https://www.xilinx.com/content/dam/xilinx/support/documents/sw_manuals/xilinx2022_2/ug953-vivado-7series-libraries.pdf
Synopsis
- iddr :: forall a dom domDDR. HasCallStack => KnownDomain dom => KnownDomain domDDR => DomainPeriod dom ~ (2 * DomainPeriod domDDR) => DomainActiveEdge dom ~ 'Rising => BitPack a => Clock dom -> Reset dom -> Enable dom -> Signal domDDR a -> Signal dom (a, a)
- oddr :: forall a dom domDDR. HasCallStack => KnownDomain dom => KnownDomain domDDR => DomainPeriod dom ~ (2 * DomainPeriod domDDR) => DomainActiveEdge dom ~ 'Rising => BitPack a => Clock dom -> Reset dom -> Enable dom -> Signal dom (a, a) -> Signal domDDR a
- iddr# :: forall n dom domDDR. HasCallStack => KnownDomain dom => KnownDomain domDDR => DomainPeriod dom ~ (2 * DomainPeriod domDDR) => DomainActiveEdge dom ~ 'Rising => KnownNat n => Clock dom -> Reset dom -> Enable dom -> Signal domDDR (BitVector n) -> Signal dom (BitVector n, BitVector n)
- oddr# :: forall n dom domDDR. HasCallStack => KnownDomain dom => KnownDomain domDDR => DomainPeriod dom ~ (2 * DomainPeriod domDDR) => DomainActiveEdge dom ~ 'Rising => KnownNat n => Clock dom -> Reset dom -> Enable dom -> Signal dom (BitVector n) -> Signal dom (BitVector n) -> Signal domDDR (BitVector n)
Documentation
Arguments
| :: forall a dom domDDR. HasCallStack | |
| => KnownDomain dom | |
| => KnownDomain domDDR | |
| => DomainPeriod dom ~ (2 * DomainPeriod domDDR) | |
| => DomainActiveEdge dom ~ 'Rising | |
| => BitPack a | |
| => Clock dom | |
| -> Reset dom | |
| -> Enable dom | |
| -> Signal domDDR a | DDR input signal |
| -> Signal dom (a, a) | Normal speed output pair |
Xilinx specific variant of ddrIn implemented using the Xilinx IDDR
primitive in SAME_EDGE mode.
Reset values are 0
Of the output pair (o0, o1), o0 is the data clocked in on the falling
edge and o1 is the data clocked in on the rising edge, and o0 comes
before o1 in time.
NB: This primitive only supports rising edges as the active edge.
Arguments
| :: forall a dom domDDR. HasCallStack | |
| => KnownDomain dom | |
| => KnownDomain domDDR | |
| => DomainPeriod dom ~ (2 * DomainPeriod domDDR) | |
| => DomainActiveEdge dom ~ 'Rising | |
| => BitPack a | |
| => Clock dom | |
| -> Reset dom | |
| -> Enable dom | |
| -> Signal dom (a, a) | Normal speed input pair |
| -> Signal domDDR a | DDR output signal |
Xilinx specific variant of ddrOut implemented using the Xilinx ODDR
primitive in SAME_EDGE mode.
Reset value is 0
Of the input pair (i0, i1), i0 is the data clocked out on the rising
edge and i1 is the data clocked out on the falling edge, and i0 comes
before i1 in time.
NB: This primitive only supports rising edges as the active edge.
Internal
iddr# :: forall n dom domDDR. HasCallStack => KnownDomain dom => KnownDomain domDDR => DomainPeriod dom ~ (2 * DomainPeriod domDDR) => DomainActiveEdge dom ~ 'Rising => KnownNat n => Clock dom -> Reset dom -> Enable dom -> Signal domDDR (BitVector n) -> Signal dom (BitVector n, BitVector n) Source #
oddr# :: forall n dom domDDR. HasCallStack => KnownDomain dom => KnownDomain domDDR => DomainPeriod dom ~ (2 * DomainPeriod domDDR) => DomainActiveEdge dom ~ 'Rising => KnownNat n => Clock dom -> Reset dom -> Enable dom -> Signal dom (BitVector n) -> Signal dom (BitVector n) -> Signal domDDR (BitVector n) Source #