DDR input primitive

Consumes a DDR input signal and produces a regular signal containing a pair of values.

Data is clocked in on both edges of the clock signal. We can discern the active edge of the clock and the other edge. When the domain has the rising edge as the active edge (which is the most common), this means that the rising edge is the active edge and the falling edge is the other edge.

Of the output pair (o0, o1), o0 is the data clocked in on the other edge and o1 is the data clocked in on the active edge, and o0 comes before o1 in time. With a domain where the rising edge is the active edge, this means o0 is clocked in on the falling clock edge and o1 is clocked in on the rising clock edge. For a domain with the falling edge as the active edge, this is the other way around, but o0 still comes before o1 in time.

>>> sampleN 5 $ ddrIn @Int @System @DDR clockGen resetGen enableGen (-1,-2,-3) (fromList [0..10])
[(-1,-2),(-1,-2),(-3,2),(3,4),(5,6)]

DDR output primitive

Produces a DDR output signal from a normal signal of pairs of input.

Data is clocked out on both edges of the clock signal. We can discern the active edge of the clock and the other edge. When the domain has the rising edge as the active edge (which is the most common), this means that the rising edge is the active edge and the falling edge is the other edge.

Of the input pair (i0, i1), i0 is the data clocked out on the active edge and i1 is the data clocked out on the other edge, and i0 comes before i1 in time. With a domain where the rising edge is the active edge, this means i0 is clocked out on the rising clock edge and i1 is clocked out on the falling clock edge. For a domain with the falling edge as the active edge, this is the other way around, but i0 still comes before i1 in time.

>>> sampleN 7 (ddrOut @Int @System @DDR clockGen resetGen enableGen (-1) (fromList [(0,1),(2,3),(4,5)]))
[-1,-1,-1,2,3,4,5]

Use a DDR output primitive to forward a clock to an output pin

This function allows outputting a clock signal on a DDR-capable output pin. As with the DDR output primitive itself, the created clock cannot be used internally in the design.

The ddrOut primitive passed in will always have its enable asserted. If the Enable input of ddrForwardClock is deasserted, the data inputs of the ddrOut primitive will switch to achieve the desired output signal. This is because the behavior of the enable input of the DDR primitive differs between vendor-specific primitives.

The Reset input of this function is passed on to the ddrOut primitive and not otherwise used by ddrForwardClock.

With the phase argument, the phase relation between input and output clock can be defined. With the argument Nothing, the clocks are in phase: the active edge of the output clock is on the active edge of the input clock, even if the domains differ on what the active edge is.

With the idle argument, the output level when the Enable input is deasserted can be defined. With Nothing, it will be 0 for a clock with the rising edge as the active edge, and 1 for a clock with the falling edge as the active edge.

NB: The deassertion of the Enable input or the assertion of the Reset input is not faithfully simulated in Haskell simulation: Haskell simulation of a Clash design has clocks that always run. The generated HDL will actually output an idle state when Enable is deasserted (and the reset depends on the ddrOut primitive used).