verismith-1.1.0: Random verilog generation and simulator testing.

Copyright	(c) 2018-2019 Yann Herklotz
License	GPL-3
Maintainer	yann [at] yannherklotz [dot] com
Stability	experimental
Portability	POSIX
Safe Haskell	None
Language	Haskell2010

Verismith.Verilog.Internal

Description

Defaults and common functions.

Synopsis

regDecl :: Identifier -> ModItem ann
wireDecl :: Identifier -> ModItem ann
emptyMod :: ModDecl ann
setModName :: Text -> ModDecl ann -> ModDecl ann
addModPort :: Port -> ModDecl ann -> ModDecl ann
addModDecl :: ModDecl ann -> Verilog ann -> Verilog ann
testBench :: ModDecl ann
addTestBench :: Verilog ann -> Verilog ann
defaultPort :: Identifier -> Port
portToExpr :: Port -> Expr
modName :: ModDecl ann -> Text
yPort :: Identifier -> Port
wire :: Range -> Identifier -> Port
reg :: Range -> Identifier -> Port

Documentation

regDecl :: Identifier -> ModItem ann Source #

wireDecl :: Identifier -> ModItem ann Source #

emptyMod :: ModDecl ann Source #

Create an empty module.

setModName :: Text -> ModDecl ann -> ModDecl ann Source #

Set a module name for a module declaration.

addModPort :: Port -> ModDecl ann -> ModDecl ann Source #

Add a input port to the module declaration.

addModDecl :: ModDecl ann -> Verilog ann -> Verilog ann Source #

testBench :: ModDecl ann Source #

addTestBench :: Verilog ann -> Verilog ann Source #

defaultPort :: Identifier -> Port Source #

portToExpr :: Port -> Expr Source #

modName :: ModDecl ann -> Text Source #

yPort :: Identifier -> Port Source #

wire :: Range -> Identifier -> Port Source #

reg :: Range -> Identifier -> Port Source #