| Copyright | (C) 2017 Google Inc 2025 QBayLogic B.V. |
|---|---|
| License | BSD2 (see the file LICENSE) |
| Maintainer | QBayLogic B.V. <devops@qbaylogic.com> |
| Safe Haskell | None |
| Language | Haskell2010 |
Clash.Xilinx.DDR
Description
DDR primitives for Xilinx FPGAs
For general information about DDR primitives see Clash.Explicit.DDR.
For more information about the Xilinx DDR primitives see:
- Vivado Design Suite 7 Series FPGA and Zynq-7000 All Programmable SoC Libraries Guide, UG953 (v2022.2) October 19, 2022, p369-371, p477-479, https://www.xilinx.com/content/dam/xilinx/support/documents/sw_manuals/xilinx2022_2/ug953-vivado-7series-libraries.pdf
Synopsis
- iddr :: forall fast fPeriod edge reset init polarity slow m. (HasCallStack, KnownConfiguration fast ('DomainConfiguration fast fPeriod edge reset init polarity), KnownConfiguration slow ('DomainConfiguration slow (2 * fPeriod) edge reset init polarity), KnownNat m) => Clock slow -> Reset slow -> Enable slow -> Signal fast (BitVector m) -> Signal slow (BitVector m, BitVector m)
- oddr :: forall fast fPeriod edge reset init polarity slow m. (KnownConfiguration fast ('DomainConfiguration fast fPeriod edge reset init polarity), KnownConfiguration slow ('DomainConfiguration slow (2 * fPeriod) edge reset init polarity), KnownNat m) => Clock slow -> Reset slow -> Enable slow -> Signal slow (BitVector m, BitVector m) -> Signal fast (BitVector m)
Documentation
Arguments
| :: forall fast fPeriod edge reset init polarity slow m. (HasCallStack, KnownConfiguration fast ('DomainConfiguration fast fPeriod edge reset init polarity), KnownConfiguration slow ('DomainConfiguration slow (2 * fPeriod) edge reset init polarity), KnownNat m) | |
| => Clock slow | |
| -> Reset slow | |
| -> Enable slow | |
| -> Signal fast (BitVector m) | DDR input signal |
| -> Signal slow (BitVector m, BitVector m) | Normal speed output pair |
Xilinx specific variant of ddrIn implemented using the Xilinx IDDR
primitive in SAME_EDGE mode.
Reset values are 0
Of the output pair (o0, o1), o0 is the data clocked in on the falling
edge and o1 is the data clocked in on the rising edge, and o0 comes
before o1 in time.
NB: This primitive only supports rising edges as the active edge. Trying to instantiate this function in a domain where falling edges are the active edge will lead to a HDL generation or Haskell simulation error.
Arguments
| :: forall fast fPeriod edge reset init polarity slow m. (KnownConfiguration fast ('DomainConfiguration fast fPeriod edge reset init polarity), KnownConfiguration slow ('DomainConfiguration slow (2 * fPeriod) edge reset init polarity), KnownNat m) | |
| => Clock slow | |
| -> Reset slow | |
| -> Enable slow | |
| -> Signal slow (BitVector m, BitVector m) | Normal speed input pair |
| -> Signal fast (BitVector m) | DDR output signal |
Xilinx specific variant of ddrOut implemented using the Xilinx ODDR
primitive in SAME_EDGE mode.
Reset value is 0
Of the input pair (i0, i1), i0 is the data clocked out on the rising
edge and i1 is the data clocked out on the falling edge, and i0 comes
before i1 in time.
NB: This primitive only supports rising edges as the active edge. Trying to instantiate this function in a domain where falling edges are the active edge will lead to a HDL generation or Haskell simulation error.