| Copyright | (C) 2017 Google Inc 2019 Myrtle Software Ltd 2025 QBayLogic B.V. |
|---|---|
| License | BSD2 (see the file LICENSE) |
| Maintainer | QBayLogic B.V. <devops@qbaylogic.com> |
| Safe Haskell | None |
| Language | Haskell2010 |
Clash.Intel.DDR
Description
DDR primitives for Intel FPGAs using ALTDDIO primitives.
For general information about DDR primitives see Clash.Explicit.DDR.
Note that a reset is only available on certain devices, see the ALTDDIO user guide for the specifics: https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/ug/ug_altddio.pdf
Synopsis
- altddioIn :: forall fast fPeriod edge reset init polarity slow m deviceFamily. (HasCallStack, KnownConfiguration fast ('DomainConfiguration fast fPeriod edge reset init polarity), KnownConfiguration slow ('DomainConfiguration slow (2 * fPeriod) edge reset init polarity), KnownNat m) => SSymbol deviceFamily -> Clock slow -> Reset slow -> Enable slow -> Signal fast (BitVector m) -> Signal slow (BitVector m, BitVector m)
- altddioOut :: forall fast fPeriod edge reset init polarity slow m deviceFamily. (HasCallStack, KnownConfiguration fast ('DomainConfiguration fast fPeriod edge reset init polarity), KnownConfiguration slow ('DomainConfiguration slow (2 * fPeriod) edge reset init polarity), KnownNat m) => SSymbol deviceFamily -> Clock slow -> Reset slow -> Enable slow -> Signal slow (BitVector m, BitVector m) -> Signal fast (BitVector m)
Documentation
Arguments
| :: forall fast fPeriod edge reset init polarity slow m deviceFamily. (HasCallStack, KnownConfiguration fast ('DomainConfiguration fast fPeriod edge reset init polarity), KnownConfiguration slow ('DomainConfiguration slow (2 * fPeriod) edge reset init polarity), KnownNat m) | |
| => SSymbol deviceFamily | The FPGA family For example this can be instantiated as follows: SSymbol @"Cyclone IV GX" |
| -> Clock slow | |
| -> Reset slow | |
| -> Enable slow | |
| -> Signal fast (BitVector m) | DDR input signal |
| -> Signal slow (BitVector m, BitVector m) | Normal speed output pair |
Intel specific variant of ddrIn implemented using the ALTDDIO_IN IP core.
Reset values are 0
Of the output pair (o0, o1), o0 is the data clocked in on the falling
edge and o1 is the data clocked in on the rising edge, and o0 comes
before o1 in time.
NB: This primitive only supports rising edges as the active edge. Trying to instantiate this function in a domain where falling edges are the active edge will lead to a HDL generation or Haskell simulation error.
Arguments
| :: forall fast fPeriod edge reset init polarity slow m deviceFamily. (HasCallStack, KnownConfiguration fast ('DomainConfiguration fast fPeriod edge reset init polarity), KnownConfiguration slow ('DomainConfiguration slow (2 * fPeriod) edge reset init polarity), KnownNat m) | |
| => SSymbol deviceFamily | The FPGA family For example this can be instantiated as follows: SSymbol @"Cyclone IV E" |
| -> Clock slow | |
| -> Reset slow | |
| -> Enable slow | |
| -> Signal slow (BitVector m, BitVector m) | Normal speed input pair |
| -> Signal fast (BitVector m) | DDR output signal |
Intel specific variant of ddrOut implemented using the ALTDDIO_OUT IP core.
Reset value is 0
Of the input pair (i0, i1), i0 is the data clocked out on the rising
edge and i1 is the data clocked out on the falling edge, and i0 comes
before i1 in time.
NB: This primitive only supports rising edges as the active edge. Trying to instantiate this function in a domain where falling edges are the active edge will lead to a HDL generation or Haskell simulation error.