- BlackBox:
    name: Clash.Xilinx.DDR.iddr#
    kind: Declaration
    type: |-
      iddr#
        :: forall n dom domDDR
         . HasCallStack                 -- ARG[0]
        => KnownDomain dom              -- ARG[1]
        => KnownDomain domDDR           -- ARG[2]
        => DomPeriod ~ 2 * ...          -- ARG[3]
        => DomEdge ~ Rising             -- ARG[4]
        => KnownNat n                   -- ARG[5]
        => Clock dom                    -- ARG[6]
        -> Reset dom                    -- ARG[7]
        -> Enable dom                   -- ARG[8]
        -> Signal domDDR (BitVector n)  -- ARG[9]
        -> Signal dom (BitVector n, BitVector n)
    template: |-
      // iddr begin
      wire ~SIGD[~GENSYM[data_pos][1]][9];
      wire ~SIGD[~GENSYM[data_neg][2]][9];
      wire ~SIGD[~GENSYM[d][3]][9];
      assign ~SYM[3] = ~ARG[9];

      genvar ~GENSYM[i][8];
      ~GENERATE
      for (~SYM[8]=0; ~SYM[8] < ~SIZE[~TYP[9]]; ~SYM[8]=~SYM[8]+1) begin : ~GENSYM[ddri_array][7]
        IDDR #(
          .DDR_CLK_EDGE("SAME_EDGE"),
          .INIT_Q1(1'b0),
          .INIT_Q2(1'b0),
          .SRTYPE(~IF ~ISSYNC[1] ~THEN "SYNC" ~ELSE "ASYNC" ~FI)
        ) ~GENSYM[~COMPNAME_IDDR][9] (
          .Q1(~SYM[1][~SYM[8]]),
          .Q2(~SYM[2][~SYM[8]]),
          .C(~ARG[6]),
          .CE(~IF ~ISACTIVEENABLE[8] ~THEN ~ARG[8] ~ELSE 1'b1 ~FI),
          .D(~SYM[3][~SYM[8]]),
          .R(~ARG[7]),
          .S(1'b0)
        );
      end
      ~ENDGENERATE

      assign ~RESULT = {~SYM[2],~SYM[1]};
      // iddr end
- BlackBox:
    name: Clash.Xilinx.DDR.oddr#
    kind: Declaration
    type: |-
      oddr#
        :: forall n dom domDDR
         . HasCallStack              -- ARG[0]
        => KnownDomain dom           -- ARG[1]
        => KnownDomain domDDR        -- ARG[2]
        => DomPeriod ~ 2 * ...       -- ARG[3]
        => DomEdge ~ Rising          -- ARG[4]
        => KnownNat n                -- ARG[5]
        => Clock dom                 -- ARG[6]
        -> Reset dom                 -- ARG[7]
        -> Enable dom                -- ARG[8]
        -> Signal dom (BitVector n)  -- ARG[9]
        -> Signal dom (BitVector n)  -- ARG[10]
        -> Signal domDDR (BitVector n)
    template: |-
      // oddr begin
      wire ~SIGD[~GENSYM[data_pos][1]][10];
      wire ~SIGD[~GENSYM[data_neg][2]][10];
      wire ~SIGD[~GENSYM[q][3]][10];

      assign ~SYM[1] = ~ARG[9];
      assign ~SYM[2] = ~ARG[10];

      genvar ~GENSYM[i][8];
      ~GENERATE
      for (~SYM[8]=0; ~SYM[8] < ~SIZE[~TYP[10]]; ~SYM[8]=~SYM[8]+1) begin : ~GENSYM[ddro_array][7]
        ODDR #(
          .DDR_CLK_EDGE("SAME_EDGE"),
          .INIT(1'b0),
          .SRTYPE(~IF ~ISSYNC[1] ~THEN "SYNC" ~ELSE "ASYNC" ~FI)
        ) ~GENSYM[~COMPNAME_ODDR][9] (
          .Q(~SYM[3][~SYM[8]]),
          .C(~ARG[6]),
          .CE(~IF ~ISACTIVEENABLE[8] ~THEN ~ARG[8] ~ELSE 1'b1 ~FI),
          .D1(~SYM[1][~SYM[8]]),
          .D2(~SYM[2][~SYM[8]]),
          .R(~ARG[7]),
          .S(1'b0)
        );
      end
      ~ENDGENERATE

      assign ~RESULT = ~SYM[3];
      // oddr end