- BlackBox:
    name: Clash.Intel.DDR.altddioIn#
    imports:
    - altera_mf.altera_mf_components.all
    kind: Declaration
    libraries:
    - altera_mf
    type: |-
      altddioIn#
        :: ( HasCallStack               -- ARG[0]
           , KnownConfi~ fast domf      -- ARG[1]
           , KnownConfi~ slow doms      -- ARG[2]
           , KnownNat m )               -- ARG[3]
        => SSymbol deviceFamily         -- ARG[4]
        -> Clock slow                   -- ARG[5]
        -> Reset slow                   -- ARG[6]
        -> Enable slow                  -- ARG[7]
        -> Signal fast (BitVector m)    -- ARG[8]
        -> Signal slow (BitVector m,BitVector m)
    template: |-
      -- altddioIn begin
      ~GENSYM[~COMPNAME_ALTDDIO_IN][0] : block
        signal ~GENSYM[dataout_l][1] : ~TYP[8];
        signal ~GENSYM[dataout_h][2] : ~TYP[8];~IF ~ISACTIVEENABLE[7] ~THEN
        signal ~GENSYM[ce_logic][4]: std_logic;~ELSE ~FI
      begin~IF ~ISACTIVEENABLE[7] ~THEN
        ~SYM[4] <= '1' when (~ARG[7]) else '0';~ELSE ~FI
        ~GENSYM[~COMPNAME_ALTDDIO_IN][7] : ALTDDIO_IN
        GENERIC MAP (
          intended_device_family => ~LIT[4],
          invert_input_clocks => "OFF",
          lpm_hint => "UNUSED",
          lpm_type => "altddio_in",
          power_up_high => "OFF",
          width => ~SIZE[~TYP[8]]
        )
        PORT MAP (~IF ~ISSYNC[6] ~THEN
          sclr      => ~ARG[6],~ELSE
          aclr      => ~ARG[6],~FI
          datain    => ~ARG[8],~IF ~ISACTIVEENABLE[7] ~THEN
          inclocken => ~SYM[4],~ELSE ~FI
          inclock   => ~ARG[5],
          dataout_h => ~SYM[2],
          dataout_l => ~SYM[1]
        );
        ~RESULT <= (~SYM[1],~SYM[2]);
      end block;
      -- altddioIn end
- BlackBox:
    name: Clash.Intel.DDR.altddioOut#
    imports:
    - altera_mf.altera_mf_components.all
    kind: Declaration
    libraries:
    - altera_mf
    type: |-
      altddioOut#
        :: ( HasCallStack             -- ARG[0]
           , KnownConfi~ fast domf    -- ARG[1]
           , KnownConfi~ slow doms    -- ARG[2]
           , KnownNat m )             -- ARG[3]
        => SSymbol deviceFamily       -- ARG[4]
        -> Clock slow                 -- ARG[5]
        -> Reset slow                 -- ARG[6]
        -> Enable slow                -- ARG[7]
        -> Signal slow (BitVector m)  -- ARG[8]
        -> Signal slow (BitVector m)  -- ARG[9]
        -> Signal fast (BitVector m)
    template: |-
      -- altddioOut begin
      ~GENSYM[~COMPNAME_ALTDDIO_OUT][0] : block ~IF ~ISACTIVEENABLE[7] ~THEN
        signal ~GENSYM[ce_logic][1] : std_logic; ~ELSE ~FI
      begin~IF ~ISACTIVEENABLE[7] ~THEN
        ~SYM[1] <= '1' when (~ARG[7]) else '0'; ~ELSE ~FI
        ~GENSYM[~COMPNAME_ALTDDIO_OUT][7] : ALTDDIO_OUT
          GENERIC MAP (
            extend_oe_disable => "OFF",
            intended_device_family => ~LIT[4],
            invert_output => "OFF",
            lpm_hint => "UNUSED",
            lpm_type => "altddio_out",
            oe_reg => "UNREGISTERED",
            power_up_high => "OFF",
            width => ~SIZE[~TYPO]
          )
          PORT MAP (~IF ~ISSYNC[2] ~THEN
            sclr       => ~ARG[6],~ELSE
            aclr       => ~ARG[6],~FI ~IF ~ISACTIVEENABLE[7] ~THEN
            outclocken => ~SYM[1],~ELSE ~FI
            outclock   => ~ARG[5],
            datain_h   => ~ARG[8],
            datain_l   => ~ARG[9],
            dataout    => ~RESULT
          );
      end block;
      -- altddioOut end
