[ { "BlackBox" :
    { "name" : "Clash.Explicit.BlockRam.blockRam#"
    , "type" :
"blockRam#
  :: HasCallStack    --       ARG[0]
  => Clock dom gated -- clk,  ARG[1]
  -> Vec n a         -- init, ARG[2]
  -> Signal dom Int  -- rd,   ARG[3]
  -> Signal dom Bool -- wren, ARG[4]
  -> Signal dom Int  -- wr,   ARG[5]
  -> Signal dom a    -- din,  ARG[6]
  -> Signal dom a"
    , "templateD" :
"-- blockRam begin
~GENSYM[~COMPNAME_blockRam][0] : block
  signal ~GENSYM[RAM][1] : ~TYP[2] := ~LIT[2];
  signal ~GENSYM[rd][3]  : integer range 0 to ~LENGTH[~TYP[2]] - 1;
  signal ~GENSYM[wr][4]  : integer range 0 to ~LENGTH[~TYP[2]] - 1;~IF ~ISGATED[1] ~THEN
  signal ~GENSYM[clk][5] : std_logic;
  signal ~GENSYM[ce][6]  : boolean;~ELSE ~FI
begin
  ~SYM[3] <= to_integer(~ARG[3])
  -- pragma translate_off
                mod ~LENGTH[~TYP[2]]
  -- pragma translate_on
                ;

  ~SYM[4] <= to_integer(~ARG[5])
  -- pragma translate_off
                mod ~LENGTH[~TYP[2]]
  -- pragma translate_on
                ;
~IF ~VIVADO ~THEN ~IF ~ISGATED[1] ~THEN
  (~SYM[5],~SYM[6]) <= ~ARG[1];
  ~GENSYM[blockRam_sync][7] : process(~SYM[5])
  begin
    if rising_edge(~SYM[5]) then
      if ~SYM[6] then
        if ~ARG[4] then
          ~SYM[1](~SYM[4]) <= ~TOBV[~ARG[6]][~TYP[6]];
        end if;
        ~RESULT <= fromSLV(~SYM[1](~SYM[3]))
        -- pragma translate_off
        after 1 ps
        -- pragma translate_on
        ;
      end if;
    end if;
  end process;~ELSE
  ~SYM[7] : process(~ARG[1])
  begin
    if rising_edge(~ARG[1]) then
      if ~ARG[4] then
        ~SYM[1](~SYM[4]) <= ~TOBV[~ARG[6]][~TYP[6]];
      end if;
      ~RESULT <= fromSLV(~SYM[1](~SYM[3]))
      -- pragma translate_off
      after 1 ps
      -- pragma translate_on
      ;
    end if;
  end process;~FI ~ELSE ~IF ~ISGATED[1] ~THEN
  (~SYM[5],~SYM[6]) <= ~ARG[1];
  ~SYM[7] : process(~SYM[5])
  begin
    if rising_edge(~SYM[5]) then
      if ~ARG[4] and ~SYM[6] then
        ~SYM[1](~SYM[4]) <= ~ARG[6];
      end if;
      if ~SYM[6] then
        ~RESULT <= ~SYM[1](~SYM[3])
        -- pragma translate_off
        after 1 ps
        -- pragma translate_on
        ;
      end if;
    end if;
  end process;~ELSE
  ~SYM[7] : process(~ARG[1])
  begin
    if rising_edge(~ARG[1]) then
      if ~ARG[4] then
        ~SYM[1](~SYM[4]) <= ~ARG[6];
      end if;
      ~RESULT <= ~SYM[1](~SYM[3])
      -- pragma translate_off
      after 1 ps
      -- pragma translate_on
      ;
    end if;
  end process;~FI ~FI
end block;
--end blockRam"
    }
  }
]