[ { "BlackBox" :
    { "name" : "Clash.Explicit.BlockRam.File.blockRamFile#"
    , "type" :
"blockRamFile#
  :: (KnownNat m, HasCallStack)-- (ARG[0],ARG]1)
  => Clock dom gated          -- clk,  ARG[2]
  -> SNat n                   -- sz,   ARG[3]
  -> FilePath                 -- file, ARG[4]
  -> Signal dom Int           -- rd,   ARG[5]
  -> Signal dom Bool          -- wren, ARG[6]
  -> Signal dom Int           -- wr,   ARG[7]
  -> Signal dom (BitVector m) -- din,  ARG[8]
  -> Signal dom (BitVector m)"
    , "templateD" :
"-- blockRamFile begin
~GENSYM[~COMPNAME_blockRamFile][0] : block
  type ~GENSYM[RamType][6] is array(natural range <>) of bit_vector(~LIT[0]-1 downto 0);

  impure function ~GENSYM[InitRamFromFile][1] (RamFileName : in string) return ~SYM[6] is
    FILE RamFile : text open read_mode is RamFileName;
    variable RamFileLine : line;
    variable RAM : ~SYM[6](0 to ~LIT[3]-1);
  begin
    for i in RAM'range loop
      readline(RamFile,RamFileLine);
      read(RamFileLine,RAM(i));
    end loop;
    return RAM;
  end function;

  signal ~GENSYM[RAM][2] : ~SYM[6](0 to ~LIT[3]-1) := ~SYM[1](~FILE[~LIT[4]]);
  signal ~GENSYM[rd][4]  : integer range 0 to ~LIT[3]-1;
  signal ~GENSYM[wr][5]  : integer range 0 to ~LIT[3]-1;~IF ~ISGATED[2] ~THEN
  signal ~GENSYM[clk][7] : std_logic;
  signal ~GENSYM[ce][8]  : boolean;~ELSE ~FI
begin
  ~SYM[4] <= to_integer(~ARG[5])
  -- pragma translate_off
                mod ~LIT[3]
  -- pragma translate_on
                ;

  ~SYM[5] <= to_integer(~ARG[7])
  -- pragma translate_off
                mod ~LIT[3]
  -- pragma translate_on
                ;
  ~IF ~VIVADO ~THEN ~IF ~ISGATED[2] ~THEN
  (~SYM[7],~SYM[8]) <= ~ARG[2];
  ~GENSYM[blockRamFile_sync][9] : process(~SYM[7])
  begin
    if rising_edge(~SYM[7]) then
      if ~SYM[8] then
        if ~ARG[6] then
          ~SYM[2](~SYM[5]) <= to_bitvector(~ARG[8]);
        end if;
        ~RESULT <= to_stdlogicvector(~SYM[2](~SYM[4]))
        -- pragma translate_off
        after 1 ps
        -- pragma translate_on
        ;
      end if;
    end if;
  end process;~ELSE
  ~SYM[9] : process(~ARG[2])
  begin
    if rising_edge(~ARG[2]) then
      if ~ARG[6] then
        ~SYM[2](~SYM[5]) <= to_bitvector(~ARG[8]);
      end if;
      ~RESULT <= to_stdlogicvector(~SYM[2](~SYM[4]))
      -- pragma translate_off
      after 1 ps
      -- pragma translate_on
      ;
    end if;
  end process;~FI ~ELSE ~IF ~ISGATED[2] ~THEN
  (~SYM[7],~SYM[8]) <= ~ARG[2];
  ~SYM[9] : process(~SYM[7])
  begin
    if rising_edge(~SYM[7]) then
      if ~ARG[6] and ~SYM[8] then
        ~SYM[2](~SYM[5]) <= to_bitvector(~ARG[8]);
      end if;
      if ~SYM[8] then
        ~RESULT <= to_stdlogicvector(~SYM[2](~SYM[4]))
        -- pragma translate_off
        after 1 ps
        -- pragma translate_on
        ;
      end if;
    end if;
  end process;~ELSE
  ~SYM[9] : process(~ARG[2])
  begin
    if rising_edge(~ARG[2]) then
      if ~ARG[6] then
        ~SYM[2](~SYM[5]) <= to_bitvector(~ARG[8]);
      end if;
      ~RESULT <= to_stdlogicvector(~SYM[2](~SYM[4]))
      -- pragma translate_off
      after 1 ps
      -- pragma translate_on
      ;
    end if;
  end process;~FI ~FI
end block;
-- blockRamFile end"
    }
  }
]